A semiconductor device having a semiconductor chip and the first to third metal layers, i.e., plates, is disclosed in Japanese Patent Application Publication No. 2003-110064. The first metal layer is bonded to the semiconductor chip through the first solder layer so that the first metal layer works as an electrode and a heat radiation plate. The second metal layer is bonded to the semiconductor chip through the second solder layer, and the second metal layer is disposed opposite to the first metal layer. The third metal layer is bonded to the second metal layer through the third solder layer, and is disposed opposite to the semiconductor chip. Thus, in the device, the first to third solder layers are disposed between the first metal layer and the semiconductor chip, between the chip and the second metal layer, and between the second and third metal layers, respectively. The first to third solder layers are formed in such a manner that a solder foil is sandwiched therebetween, and then, the solder foil is heated up to melting point of the solder. Thus, the solder foil is melted so that two parts are bonded together with the solder.
However, in each solder layer, the supplied amount of the solder foil is in short or excess. This is because variations of dimensions of the semiconductor chip and/or the metal layers may cause excess or deficiency of the solder. Specifically, the volume of the solder foil may be in short or excess. When the volume of the solder is excess, the excess solder overflows so that the excess solder is adhered to other parts of the device such as a wire. Thus, an electric circuit may be short. Thus, the excess solder adheres to the other parts so that a solder bridge is formed. Accordingly, the device may be damaged. On the other hand, when the volume of the solder is in short, the thickness of the solder layer is not sufficient. Therefore, reliability of bonding is reduced. Further, heat radiation performance is also reduced.